WAFER LEVEL PROCESS FORMATION OF A POLYMER ISOLATED …

Loading...

Taking too long?

Reload document

| Open in new tab

Presented to the Santa Clara Valley Chapter,
IEEE CPMT Society
Tuesday, November 22, 2016

Harry Gee

ON Semiconductor

WAFER LEVEL PROCESS FORMATION OF A
POLYMER ISOLATED CHIP SCALE PACKAGE

 Small Silicon CSP device
 Assembly Issue
 Polymer Isolation Process Module
 Experimental Results
 Conclusion
 Q & A

• 2 Lead Chip Scale Package 0201/01005 sized devices

• 100% of the CSP area is the silicon

• Using a 01005 sized CSP device occupies less board area
compared to the same sized die built in a plastic molded
package

01005

0201

01005 sized CSP

More than Two Thousand 01005

•
parts able to fit on top of a dime

• Dime thicker than six 01005 parts

Dime Diameter: 17.91 mm
Dime Thickness: 1.35 mm

Solder Bridge on the CSP end
(CSP tilted at the end)

Solder Bridge on CSP side
(CSP tilted to one side)

Solder Paste

Silicon

Low Profile Bump

Copper

Copper

Short/Leakage contributing factors
• Short Bump Height (Low Profile)
• Solder Paste Proximity to CSP Edge
• Solder Stencil to Pad Alignment
• CSP placement accuracy and tilt

Excess Solder (Short between bare
silicon die sidewall and the PCB
pad)

CSP

Solder

Silicon

Solder

0201 CSP Tilt
(Sidewall Bridging)

Close up image
Of sidewall Solder Bridging

Short causes assembly rework and added cost

Silicon

Top Metal

Passivation
Solder Bump

Polymer Isolation

Silicon

Top Metal
Passivation
Solder Bump

Conventional Bare Silicon CSP

5-Side Polymer Isolated CSP

• About 70% of a 0201/01005 CSP area is available for silicon circuits
• Area lost due from the saw street region
• Silicon removed from the saw street & replaced with a polymer
• No lost in silicon real estate area with the addition of the polymer isolation
• Polymer Isolation on silicon sidewall prevents the assembly short issue
• Polymer on the backside prevents short to the silicon backside